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toshiba toshiba corporation 1/22 tlcs-90 series TMP90PM38 the information contained here is subject to change without notice. the information contained herein is presented only as guide for the applications of our products. no responsibility is assumed by toshiba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of toshiba or others. these toshiba products are intended for usage in general electronic equipments (of?e equipment, communication equipment, measuring equipment, domestic electri?ation, etc.) please make sure that you consult with us before you use these toshiba products in equip- ments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traf? signal, combustion control, all types of safety devices, etc.). toshiba cannot accept liability to any damage which may occur in case these toshiba products were used in the mentioned equipments without prior consultation with toshiba. cmos 8?it microcontrollers TMP90PM38f/TMP90PM38t 1. outline and characteristics the TMP90PM38 is a system evaluation lsi having a built-in one-time prom (16k byte) for tmp90cm38. a programming and veri?ation for the internal prom is acheived by using a general eprom programmer with an adapter socket. the function of this device is exactly the same as the tmp90cm36 by programming to internal prom: parts no. rom ram package adapter socket no. TMP90PM38f otp 32968 x 8bit 1024 x 8bit 80-fp under development TMP90PM38t 84-qfj (plcc)
2/22 toshiba corporation TMP90PM38 figure 1. TMP90PM38 block diagram
toshiba corporation 3/22 TMP90PM38 2. pin assignment and functions the assignment of input/output pins for TMP90PM38, their names and functions are described below. 2.1 pin assignment figure 2.1 (1) shows pin assignment of the TMP90PM38f. figure 2.1 (1). pin assignments (flat package)
4/22 toshiba corporation TMP90PM38 figure 2.1 (2) shows the pin assignment of TMP90PM38. figure 2.1 (2). pin assignments (qfj (plcc) package)
toshiba corporation 5/22 TMP90PM38 2.2 pin names and functions the TMP90PM38 has mcu mode and prom mode. (1) mcu mode (the tmp90cm36 is pin compatible). table 2.2 (1/3)
6/22 toshiba corporation TMP90PM38 table 2.2 (2/3)
toshiba corporation 7/22 TMP90PM38 table 2.2 (3/3)
8/22 toshiba corporation TMP90PM38 (2) prom mode pin functions pin disposal table 2.2 (2) prom mode name and function, pin disposal
toshiba corporation 9/22 TMP90PM38 3. operation the TMP90PM38 is the otp version of the tmp90cm38 that is replaced an internal rom from mask rom to eprom. refer to the TMP90PM38 except for the functions which are not described in this section. the following is an explanation of the hardware con?ura- tion and operation in relation to the tmp90cm38. the TMP90PM38 has an mcu mode and a prom mode. 3.1 mcu mode (1) mode setting and function the mcu mode is set by opening the clk pin (output status). in the mcu mode, the operation is the same as that of tmp90cm38. (2) memory map figure 3.1 show the memory map of tmp90cm38 and TMP90PM38. figure 3.1. TMP90PM38 and tmp90cm38 memory map
10/22 toshiba corporation TMP90PM38 3.2 prom mode (1) mode setting and function prom mode is set by setting the reset and clk pins to the ??level. the programming and veri?ation for the internal prom is acheived by using a general eprom pro- grammer with the adapter socket. the device selection (rom type) should be ?c571000d?with the following conditions. size: 1m bit (128k x 8bit), vpp: 12.75v 0.25v, tpw: 0.1ms vcc: 6.25 0.25v figure 3.2 shows the setting of pins in prom mode. figure 3.2. prom mode pin setting
toshiba corporation 11/22 TMP90PM38 (2) programming flow chart the programming mode is set by applying 12.75v (programming voltage) to the vpp pin when the follow- ing pins are set as follows. (vcc: 6.25v) *these conditions can be obtained (reset : ??level) by using adapter socket. (clk: ??level) after the address and data have been ?ed, a data on the data bus is programmed when the pgm pin is set to ?ow?(0.1ms plus is required). general programming procedure of an eprom pro- grammer is as follows. ?write data to a speci?d address for 0.1ms. ?verify the data. if the read-out data does not match the expected data, another writing is performed until the correct data is written (max. 25 times). then, verify the data and increment the address. the veri?ation for all data is done under the condition of v pp = v cc = 5v after all data were written. figure 3.3 shows the programming ?wchart. (3) the security bit the TMP90PM38 has the security bit in prom cell. if the security bit is programmed to ?? the content of the prom is disable to read in prom mode. how to program the security bit in the prom mode (1) connect p40 pin to v cc (2) set a0 ~ a16 to ??respectively (3) set the 8-bit data to ?e h
12/22 toshiba corporation TMP90PM38 (4) programming flowchart figure 3.3. programming flowchart
toshiba corporation 13/22 TMP90PM38 4. electrical characteristics (preliminary) TMP90PM38f/TMP90PM38t 4.1 absolute maximum ratings symbol item rating unit v cc power supply voltage -0.5 ~ + 7 v v in input voltage -0.5 ~ v cc + 0.5 v ? iol output current (total) 100 ma ? iol output current (total) -70 p d power dissipation (ta = 85 c) f 500 mw t 600 t solder soldering temperature (10s) 260 c t stg storage temperature -65 ~ 150 c t opr operating temperature -40 ~ 85 c 4.2 dc characteristics v cc = 5v 10% ta = -20 ~ 70 c (1 ~ 16mhz) typical values are for ta = 25 c and vcc = 5v. symbol item min max unit test conditions v il input low voltage (p0) -0.3 0.8 v v il1 p1, p2, p3, p4, p5, p6, p7. p9, p10 -0.3 0.3v cc v v il2 reset , p81 (int0), p82 (stby ) (nmi ) -0.3 0.25v cc v v il3 ea -0.3 0.3 v v il4 x1 -0.3 0.2v cc v v ih input high voltage (p0) 2.2 v cc + 0.3 v v ih1 p1, p2, p3, p4, p5, p6, p7. p9, p10 0.7v cc v cc + 0.3 v v ih2 reset , p81 (int0), p82 (stby ) (nmi ) 0.75v cc v cc + 0.3 v v ih3 ea v cc -0 .3 v cc + 0.3 v v ih4 x1 0.8v cc v cc + 0.3 v v ol output low voltage 0.45 v i ol = 1.6ma v oh v oh1 v oh2 output high voltage 2.4 0.75v cc 0.9v cc v v v i oh = -400 m a i oh = -100 m a i oh = -20 m a i dar darlington drive current (8 i/o pins max) -1.0 -3.5 ma v ext = 1.5v r ext = 1.1k w i li input leakage current 0.02 (typ) 5 m a 0.0 vin v cc i lo output leakage current 0.05 (typ) 10 m a 0.2 vin v cc - 0.2 i cc operating current (run) idle 35 (typ) 1.5 (typ) 50 5 ma ma tosc = 16mhz stop (ta = -20 ~ 70 c) stop (ta = 0 ~ 50 c) 0.2 (typ) 40 10 m a m a 0.2 vin v cc - 0.2 v stop power down voltage (@stop) (ram back up) 2.0 6.0 v v il2 = 0.2v cc , v ih2 = 0.8v cc r rst reset pull up register 50 150 k w c io pin capacitance 10 pf testfreq = 1mhz v th schmitt width reset , p81, p82) 0.4 1.0 (typ) v
14/22 toshiba corporation TMP90PM38 ac measuring conditions output level: high 2.2v/low 0.8v, c l = 50pf (however, cl = 100pf for ad0 ~ 7, a8 ~ 15, ale, rd , wr ) input level: high 2.4v/low 0.45v (ad0 ~ ad7) high 0.8v cc /low 0.2v cc (excluding ad0 ~ ad7) high 0.8v cc /low 0.2v cc (excluding ad0 ~ ad7) 4.3 ac characteristics v cc = 5v 10% ta = -20 ~ 70 c (1 ~ 16mhz) symbol parameter variable 12.5mhz clock 16mhz clock unit min max min max min max t osc oscillation cycle ( = x) 62.5 1000 80 62.5 ns t cyc clk period 4x 4x 320 250 ns t wh clk high width 2x - 40 120 85 ns t wl clk low width 2x - 40 120 85 ns t al a0 ~ 7 effective address ? ale fall 0.5x - 15 25 16 ns t la ale fall ? a0 ~ 7 hold 0.5x - 15 25 16 ns t ll ale pulse width x - 40 40 23 ns t lc ale fall ? rd /wr fall 0.5x - 30 10 1 ns t cl rd /wr ? ale rise 0.5x - 20 20 11 ns t acl a0 ~ 7 effective address ? rd /wr fall x - 25 55 38 ns t ach upper effective address ? rd /wr fall 1.5x - 50 70 44 ns t ca rd /wr fall ? upper address hold 0.5x - 20 20 11 ns t adl a0 ~ 7 effective address ? effective data input 3.0x - 35 205 153 ns t adh upper effective address ? effective data input 3.5x - 55 225 164 ns t rd rd fall ? effective data input 2.0x - 50 110 75 ns t rr rd pulse width 2.0x - 40 120 85 ns t hr rd rise ? data hold 0 0?ns t rae rd rise ? address enable x - 15 65 48 ns t ww wr pulse width 2.0x - 40 120 85 ns t dw effective data ? wr rise 2.0x - 50 110 75 ns t wd wr rise ? effective data hold 0.5x - 10 30 21 ns t ackh upper address ? clk fall 2.5x - 50 150 106 ns t ackl lower address ? clk fall 2.0x - 50 110 75 ns t ckha clk fall ? upper address hold 1.5x - 80 40 13 ns t cck rd /wr ? clk fall x - 25 55 37 ns t ckhc clk fall ? rd /wr rise x - 60 20 2 ns t dck valid data clk fall x - 50 30 12 ns t cwa rd /wr fall ? valid wait x - 40 40 - 22 ns t awal lower address ? valid wait 2.0x - 70 90 - 55 ns t wah clk fall ? valid wait hold 0 0?ns t awah upper address ? valid wait 2.5x - 70 - 130 86 ns t cpw clk fall ? port data output x + 200 - 280 262 ns t prc port data input ? clk fall 200 200 200 ns t cpr clk fall ? port data hold 100 100 100 ns
toshiba corporation 15/22 TMP90PM38 4.4 a/d conversion characteristics v cc = 5v 10% ta = -20 ~ 70 c f = 1 ~ 16mhz symbol item condition min max unit v ref analog reference voltage vcc - 1.5 vcc vcc v a gnd analog reference voltage vss vss vss v ain analog input voltage range vss vcc iref analog reference voltage power supply current 0.5 1.0 ma error (quantize error of 0.5 lsb not included) total error (ta = 25 c, vcc = v ref = 5.0v) 1.0 lsb total error 2.5 4.5 timer/counter input clock (ti2, ti4) v cc = 5v 10% ta = -20 ~ 70 c f = 1 ~ 16mhz symbol item variable 12.5mhz clock 16mhz clock unit min max min max min max t vck clock cycle 8x + 100 740 600 ns t vckl low clock pulse width 4x + 40 360 290 ns t vckh high clock pulse width 4x + 40 360 290 ns 4.6 interrupt operation v cc = 5v 10% ta = -20 ~ 70 c f = 1 ~ 16mhz symbol item variable 12.5mhz clock 16mhz clock unit min max min max min max t intal int0 low level pulse width 4x 320 250 ns t intah int0 high level pulse width 4x 320 250 ns t intbl int1, int2 low level pulse width 8x + 100 740 600 ns t intbh int1, int2 high level pulse width 8x + 100 740 600 ns
16/22 toshiba corporation TMP90PM38 (2) sclk1 output mode 4.7 serial channel sio1 timing - i/o interface mode (1) sclk1 input mode v cc = 5v 10% ta = -20 ~ 70 c f = 1 ~ 16mhz symbol item variable 12.5mhz clock 16mhz clock unit min max min max min max t scy sclk1 cycle 16x 1.28 1 m s t oss output data ? rising edge of sclk t scy /2 - 5x - 50 190 137 ns t ohs sclk1 rising edge ? output data hold 5x - 100 300 212 ns t hsr sclk1 rising edge ? input data hold 0 0?ns t srd sclk1 rising edge ? effective data input t scy - 5x - 100 780 587 ns symbol parameter variable 12.5mhz clock 16mhz clock unit min max min max min max t scy sclk cycle (programmable) 16x 8192x 1.28 655.4 1 512 m s t oss output data setup ? sclk rising edge t scy - 2x - 50 970 725 ns t ohs sclk rising edge ? output data hold 2x - 80 80 45 ns t hsr sclk rising edge ? input data hold 0 0?ns t srd sclk rising edge ? effective data input t scy - 2x - 150 970 725 ns
toshiba corporation 17/22 TMP90PM38 4.8 serial channel sio2 timing 4.9 read operation (prom mode) dc characteristic, ac characteristic tcyc = 250ns (16mhz clock) a = 100ns 4.10 programming operation (prom mode) dc characteristic, ac characteristic v cc = 5v 10% ta = -20 ~ 70 c f = 1 ~ 16mhz symbol parameter condition 16mhz clock variable unit min max min max t scr serial port clock cycle time internal 500 16000 8x 256x ns external 1000 600 t scl sclk2 low width internal 200 300 4x - 50 ns external 980 1020 16x - 20 t sch sclk2 high width internal 200 300 4x - 50 ns external 980 1020 16x - 20 t skdo sclk2 ? txd2 (output data) delay time internal 112.5 x + 50 ns external 475 6x + 100 t srd sclk2 rising edge to input data valid internal 377.5 7x - 60 ns external 1150 20x - 100 t hsr input data hold after sclk2 rising edge internal 162.5 x - 100 ns external 475 6x + 100 ta = -20 ~ 70 c v cc = 5v 10% symbol parameter condition min max unit v pp v ih1 v il1 v pp read voltage input high voltage (a0 ~ a15, ce , oe , pgm ) input low voltage (a0 ~ a15, ce , oe , pgm ) 4.5 0.7 x v cc -0.3 5.5 v + 0.3 0.3 x v cc v v v t acc address to output delay c l = 50 p f 2.25tcyc + a ?s ta = 25 5 c v cc = 6.25v 0.25v symbol parameter condition min typ max unit v pp v ih v il v pp v ih v il v il programming algorithm input high voltage (d0 ~ d7) input low voltage (d0 ~ d7) input high voltage (a0 ~ a15, ce , oe , pgm ) input low voltage (a0 ~ a15, ce , oe , pgm ) v cc supply current v pp supply current t osc = 12.75mhz v pp = 13.00v 12.50 0.2v cc + 1.1 -0.3 0.7v cc -0.3 12.75 13.00 v cc + 0.3 0.2v cc - 0.1 v cc + 0.3 0.3v cc 50 50 v v v v v ma ma t pw ce program pulse width c l = 50 p f 0.095 0.1 0.105 ms
18/22 toshiba corporation TMP90PM38 4.11 timing chart
toshiba corporation 19/22 TMP90PM38 4.12 serial channel sio1 i/o interface mode timing chart
20/22 toshiba corporation TMP90PM38 4.13 serial channel sio2 timing chart
toshiba corporation 21/22 TMP90PM38 4.14 read operation timing chart (prom mode)
22/22 toshiba corporation TMP90PM38 4.15 program operationtiming chart (prom mode) high speed program formula

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